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www.latticesemi.com 1 clk5500_06.1 february 2005 data sheet ?2005 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. ispclock 5500 family in-system programmable clock generator with universal fan-out buffer features 10mhz to 320mhz input/output operation low output to output skew (<50ps) low jitter peak-to-peak(<70ps) up to 20 programmable fan-out buffers programmable output standards and individual enable controls - lvttl, lvcmos, hstl, sstl, lvds, lvpecl programmable precision output impedance - 40 to 70 ? in 5 ? increments programmable slew rate up to 10 banks with individual v cco and gnd - 1.5v, 1.8v, 2.5v, 3.3v fully integrated high-performance pll programmable lock detect multiply and divide ratio controlled by - input divider (5 bits) - internal feedback divider (5 bits) - five output dividers (5 bits) programmable on-chip loop filter precision programmable phase adjustment (skew) per output 16 settings; minimum step size 195ps - locked to vco frequency up to +/- 12ns skew range coarse and ?e adjustment modes up to five clock frequency domains flexible clock reference inputs programmable input standards - lvttl, lvcmos, sstl, hstl, lvds, lvpecl clock a/b selection multiplexer programmable precision termination four user-programmable pro?es stored in e 2 cmos memory supports both test and multiple operating con?urations full jtag boundary scan test in-system programming support exceptional power supply noise immunity commercial (0 to 70?) and industrial (-40 to 85?) temperature ranges 100-pin and 48-pin tqfp packages applications circuit board common clock generation and distribution pll-based frequency generation high fan-out clock buffer product family block diagram vco output drivers skew control m n jtag interface & e 2 cmos memory lock detect reference inputs filter phase/ frequency detector 1 023 multiple profile management logic internal feedback path pll core output routing matrix v0 v1 v2 v3 v4 output dividers * * input available only on ispclock 5520 bypass mux clock outputs
lattice semiconductor ispclock5500 family data sheet 2 general description and overview the ispclock5510 and ispclock5520 are in-system-programmable high-fanout pll-based clock drivers designed for use in high performance communications and computing applications. the ispclock5510 provides up to 10 sin- gle-ended or ?e differential clock outputs, while the ispclock5520 provides up to 20 single-ended or 10 differential clock outputs. each pair of outputs may be independently con?ured to support separate i/o standards (lvds, lvpecl, lvttl, lvcmos, sstl, hstl) and output frequency. in addition, each output provides independent pro- grammable control of termination, slew-rate, and timing skew. all con?uration information is stored on-chip in non- volatile e 2 cmos memory. the ispclock5500s pll and divider systems supports the synthesis of clock frequencies differing from that of the reference input through the provision of programmable input and feedback dividers. a set of ?e post-pll v-divid- ers provides additional ?xibility by supporting the generation of ?e separate output frequencies. loop feedback may be taken from the output of any of the ?e v-dividers. the core functions of all members of the ispclock5500 family are identical, the differences between devices being restricted to the number of inputs and outputs, as shown in the following table. figures 1 and 2 show functional block diagrams of the ispclock5510 and ispclock5520. table 1. ispclock5500 family members figure 1. ispclock5510 functional block diagram device ref. input pairs clock outputs ispclock5510 1 10 ispclock5520 2 20 vco loop filter phase detect lock detect m n input divider feedback skew adjust 1 0 feedback divider goe oex lock pll_bypass jtag interface oey tdi tms tck tdo sgate skew control output drivers bank_3a bank_3b bank_4a bank_4b output dividers output routing matrix reset v1 v2 v0 v3 v4 bank_0a bank_0b bank_1a bank_1b bank_2a bank_2b ps0 ps1 profile select control 0123 output enable controls (1-32) (1-32) (2-64) (2-64) (2-64) (2-64) (2-64) refa+ refa- refvtt
lattice semiconductor ispclock5500 family data sheet 3 figure 2. ispclock5520 functional block diagram 0 1 vco loop filter phase detect lock detect m n input divider refa+ refa- refb+ refb- refsel refvtt feedback skew adjust 1 0 feedback divider goe oex lock pll_bypass jtag interface oey tdi tms tck tdo sgate skew control output drivers skew control output drivers bank_5a bank_5b bank_6a bank_6b bank_7a bank_7b bank_8a bank_8b bank_9a bank_9b output dividers output routing matrix reset v1 v2 v0 v3 v4 bank_0a bank_0b bank_1a bank_1b bank_2a bank_2b bank_3a bank_3b bank_4a bank_4b ps0 ps1 profile select control 0123 output enable controls (1-32) (1-32) (2-64) (2-64) (2-64) (2-64) (2-64)
lattice semiconductor ispclock5500 family data sheet 4 absolute maximum ratings ispclock5500v core supply voltage v ccd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5v pll supply voltage v cca . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5v jtag supply voltage v ccj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5v output driver supply voltage v cco . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5v output voltage 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5v storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150? junction temperature with power supplied . . . . . . . . . . . . . . . . . . . -40 to 130? 1. when applied to an output when in high-z condition recommended operating conditions recommended operating conditions ?v cco vs. logic standard e 2 cmos memory write/erase characteristics symbol parameter conditions ispclock5500v units min. max. v ccd core supply voltage 3.0 3.6 v v ccj jtag i/o supply voltage 1.62 3.6 v v cca analog supply voltage 3.0 3.6 v v ccaslew v cca turn-on ramp rate 0.033 v/? t jop operating junction temperature commercial 0 100 ? industrial -40 115 t a ambient operating temperature commercial 0 70 1 ? industrial -40 85 1 1. device power dissipation may also limit maximum ambient operating temperature. v cco (v) v ref (v) v tt (v) logic standard min. typ. max. min. typ. max. min. typ. max. lvttl 3.0 3.3 3.6 lvcmos 1.8v 1.71 1.8 1.89 lvcmos 2.5v 2.375 2.5 2.625 lvcmos 3.3v 3.0 3.3 3.6 sstl2 class 1 2.375 2.5 2.625 1.15 1.25 1.35 v ref - 0.04 v ref + 0.04 sstl3 class 1 3.0 3.3 3.6 1.30 1.50 1.70 v ref - 0.05 v ref v ref + 0.05 hstl class 1 1.425 1.5 1.575 0.68 0.75 0.90 0.5 x v cco lvpecl (differential) 3.0v 3.3v 3.6v lvds v cco = 2.5v 2.375 2.5v 2.625 v cco = 3.3v 3.0 3.3 3.6 note: denotes v ref or v tt not applicable to this logic standard parameter conditions min. typ. max. units erase/reprogram cycles 1000
lattice semiconductor ispclock5500 family data sheet 5 performance characteristics ?power supply dc electrical characteristics ?single-ended logic dc electrical characteristics ?lvds symbol parameter conditions typ. max. units i ccd core supply current ispclock5510, f vco = 640mhz 100 110 ma ispclock5520, f vco = 640mhz 130 150 ma i cca analog supply current f vco = 640mhz 5.5 7 ma i cco output driver supply current (per bank) v cco = 1.8v 1 , lvcmos v cco = 2.5v 1 , lvcmos v cco = 3.3v 1 , lvcmos v cco = 3.3v 2 , lvds 13 18 24 7.5 15 24 35 8 ma i ccj jtag i/o supply current (static) v ccj = 1.8v v ccj = 2.5v v ccj = 3.3v 200 300 300 300 400 400 ? 1. supply current consumed by each bank, both outputs active, 18pf load, 320mhz output frequency. 2. supply current consumed by each bank, 100 ? /5pf differential load, 320mhz output frequency. logic standard v il (v) v ih (v) v ol max. (v) v oh min. (v) i ol (ma) i oh (ma) min. max. min. max. lvttl/lvcmos 3.3v -0.3 0.8 2 3.6 0.4 v cco - 0.4 4 1 -4 1 lvcmos 1.8v -0.3 0.68 1.07 3.6 0.4 v cco - 0.4 4 1 -4 1 lvcmos 2.5v -0.3 0.7 1.7 3.6 0.4 v cco - 0.4 4 1 -4 1 sstl2 class 1 -0.3 v ref - 0.18 v ref + 0.18 3.6 0.54 2 v cco - 0.81 2 7.6 -7.6 sstl3 class 1 -0.3 v ref - 0.2 v ref + 0.2 3.6 0.9 2 v cco - 1.3 2 8-8 hstl class 1 -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 3 v cco - 0.4 3 8-8 1. speci?d for 50 ? internal series output termination. 2. speci?d for 40 ? internal series output termination. 3. speci?d for 20 ? internal series output termination. symbol parameter conditions min. typ. max. units v icm common mode input voltage v thd 100mv v thd /2 2.0 v v thd 150mv v thd /2 2.325 v v thd differential input threshold ?00 mv v in input voltage 0 2.4 v v oh output high voltage r t = 100 ? 1.375 1.60 v v ol output low voltage r t = 100 ? 0.9 1.03 v v od output voltage differential r t = 100 ? 250 400 480 mv ? v od change in v od between h and l 50 mv v os output voltage offset common mode output voltage 1.125 1.20 1.375 v ? v os change in v os between h and l 50 mv i sa output short circuit current v od = 0v, outputs shorted to gnd 24 ma i sab output short circuit current v od = 0v, outputs shorted to each other 12 ma
lattice semiconductor ispclock5500 family data sheet 6 dc electrical characteristics ?differential lvpecl dc electrical characteristics ?input/output loading symbol parameter test conditions min. typ. max. units v ih input voltage high v ccd = 3.0 to 3.6v v ccd - 1.17 v ccd - 0.88 v v ccd = 3.3v 2.14 2.42 v il input voltage low v ccd = 3.0 to 3.6v v ccd - 1.81 v ccd - 1.48 v v ccd = 3.3v 1.49 1.83 v oh output high voltage 1 v cco = 3.0 to 3.6v v cco - 1.07 v cco - 0.88 v v cco = 3.3v 2.23 2.42 v ol output low voltage 1 v cco = 3.0 to 3.6v v cco - 1.81 v cco - 1.62 v v cco = 3.3v 1.49 1.68 1. 100 ? differential termination. symbol parameter conditions min. typ. max. units i lk input leakage note 1 ?0 ? i pu input pull-up current note 2 80 120 ? i pd input pull-down current note 3 120 150 ? i olk tristate leakage output note 4 ?0 ? c in input capacitance notes 2, 3, 5 8 10 pf note 6 13.5 15 pf 1. applies to clock reference inputs when termination ?pen? 2. applies to tdi, tms inputs. 3. applies to refsel, ps0, ps1, goe , sgate and pll_bypass. 4. applies to all logic types when in tristated mode. 5. applies to oex, oey, tck, reset inputs. 6. applies to refa+, refa-, refb+, refb-.
lattice semiconductor ispclock5500 family data sheet 7 switching characteristics ?timing adders for i/o modes output rise and fall times ?typical values 1, 2 adder type base parameter(s) description min. typ. max. units t ioi input adders 2 lvttl_in using lvttl standard 0 ns lvcmos18_in using lvcmos 1.8v standard 0 ns lvcmos25_in using lvcmos 2.5v standard 0 ns lvcmos33_in using lvcmos 3.3v standard 0 ns sstl2_in using sstl2 standard 0.4 ns sstl3_in using sstl3 standard 0.4 ns hstl_in using hstl standard 0.4 ns lvds_in using lvds standard 1.8 ns lvpecl_in using lvpecl standard 1.8 ns t ioo output adders 1, 3 lvttl_out output con?ured as lvttl buffer 0.1 ns lvcmos18_out output con?ured as lvcmos 1.8v buffer 0.1 ns lvcmos25_out output con?ured as lvcmos 2.5v buffer 0.1 ns lvcmos33_out output con?ured as lvcmos 3.3v buffer 0.1 ns sstl2_out output con?ured as sstl2 buffer 0.1 ns sstl3_out output con?ured as sstl3 buffer 0.1 ns hstl_out output con?ured as hstl buffer 0.1 ns lvds_out output con?ured as lvds buffer 0.1 ns lvpecl_out output con?ured as lvpecl buffer 0 ns t ios output slew rate adders 1 slew_1 output slew_1 (fastest) 0 ps slew_2 output slew_2 330 ps slew_3 output slew_3 660 ps slew_4 output slew_4 (slowest) 1320 ps 1. measured under standard output load conditions ?see figures 3-5. 2. all input adders referenced to lvttl. 3. all output adders referenced to lvpecl. output type slew 1 (fastest) slew 2 slew 3 slew 4 (slowest) units t r t f t r t f t r t f t r t f lvttl 0.65 0.45 0.85 0.60 1.20 0.90 1.75 1.30 ns lvcmos 1.8v 0.90 0.40 1.05 0.50 1.40 0.80 2.00 1.20 ns lvcmos 2.5v 0.70 0.40 0.90 0.55 1.20 0.85 1.80 1.20 ns lvcmos 3.3v 0.65 0.45 0.85 0.60 1.20 0.90 1.75 1.30 ns sstl2 0.65 0.40 0.90 0.60 1.35 0.85 2.30 1.40 ns sstl3 0.65 0.40 0.90 0.60 1.35 0.85 2.30 1.40 ns hstl 0.85 0.30 1.00 0.50 1.50 0.70 2.55 1.10 ns lvds 3 0.25 0.20 ns lvpecl 3 0.20 0.20 ns 1. see figures 3-5 for test conditions. 2. measured between 20% and 80% points. 3. only the ?astest slew rate is available in lvds and lvpecl modes.
lattice semiconductor ispclock5500 family data sheet 8 output test loads figures 3-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and other selected parameters as noted in the various tables of this data sheet. figure 3. cmos termination load figure 4. hstl/sstl termination load figure 5. lvds/lvpecl termination load ispclock scope 950 ? 50 ? /3" 50 ? /36" 50 ? 5pf zo = 50 ? ispclock scope 50 ? /3" 50 ? /36" 950 ? 50 ? 5pf zo = hstl: ~20 ? sstl: 40 ? vterm 50 ? ispclock 50 ? /36" 34 ? 34 ? 50 ? /36" 0.1u 0.1u 44.2 ? 3pf (parasitic) 3pf (parasitic) scope 50 ? 50 ? 5pf 5pf cha chb 50 ? /3" 50 ? /1" 50 ? /3" 50 ? /1" interface circuit 33.2 ? 33.2 ?
lattice semiconductor ispclock5500 family data sheet 9 programmable input and output termination characteristics symbol parameter conditions v cco voltage min. typ. max. units r in input resistance rin=40 ? setting 36 44 ? rin=45 ? setting 40.5 49.5 rin=50 ? setting 45 55 rin=55 ? setting 49.5 60.5 rin=60 ? setting 54 66 rin=65 ? setting 59 71.5 rin=70 ? setting 61 77 r out output resistance 1 rout 20 ? setting vcco=3.3v 14 ? vcco=2.5v 14 vcco=1.8v 14 vcco=1.5v 14 rout 40 ? setting vcco=3.3v -9% 38 9% vcco=2.5v -11% 40 11% vcco=1.8v -13% 40 13% rout 45 ? setting vcco=3.3v -10% 45 10% vcco=2.5v -12% 45 12% vcco=1.8v -14% 44 14% rout 50 ? setting vcco=3.3v -8% 50 8% vcco=2.5v -9% 49 9% vcco=1.8v -13% 49 13% rout 55 ? setting vcco=3.3v -9% 55 9% vcco=2.5v -11% 55 11% vcco=1.8v -13% 55 13% rout 60 ? setting vcco=3.3v -8% 59 8% vcco=2.5v -9% 59 9% vcco=1.8v -14% 59 14% rout 65 ? setting vcco=3.3v -8% 65 8% vcco=2.5v -9% 64 9% vcco=1.8v -13% 64 13% rout 70 ? setting vcco=3.3v -9% 72 9% vcco=2.5v -10% 70 10% vcco=1.8v -12% 69 12% 1. guaranteed by characterization.
lattice semiconductor ispclock5500 family data sheet 10 performance characteristics ?pll symbol parameter conditions min. typ. max. units f ref reference input frequency range 10 320 mhz t clockhi, t clocklo reference input clock high and low times 1.25 ns t rinp, t finp input rise and fall times measured between 20% and 80% levels 5 ns m div m-divider range 1 32 n div n-divider range 1 32 f pfd phase detector input frequency range 2 10 320 mhz f vco vco operating frequency 320 640 mhz v div output divider range even integer values only 2 64 f out output frequency range 1 fine skew mode, f vco = 640mhz 10 320 mhz coarse skew mode, f vco = 640mhz 5 160 mhz t jit (cc) output adjacent-cycle jitter 1000 cycle sample 3 55 70 ps (p-p) t jit (per) output period jitter 10000 cycle sample 3 11 14 ps (rms) t jit( ) reference clock to output jitter 6000 cycle sample 3 170 ps (rms) t static phase offset pfd input frequency 100mhz 5 -500 ps dc err output duty cycle error (see table 3 for nominal values) 4 output type lvds, v cco = 3.3v 6 260 ps output type lvcmos 3.3v 6 f out > 100 mhz 300 ps t co_bypass reference clock to output delay, pll bypass mode inputs and outputs con?ured to lvcmos 3.3v standard ? ns t l pll lock time from power-up event 150 500 ? from reset event 15 50 s psr power supply rejection, period jitter vs. power supply noise f in = f out = 100mhz vcca = vccd = vcco modulated with 100khz sinusoidal stimulus 0.05 1. in pll bypass mode (pll_bypass = high), output will support frequencies down to 0hz (divider chain is a fully static design). 2. dividers should be set so that they provide the phase detector with signals of 10mhz or greater for loop stability. 3. f in = f out = 100 mhz, m = n = 1, v = 6, output type lvpecl. 4. variation in duty cycle expressed in ps. to obtain duty cycle percentage error (% err ) for a given output frequency (f out ), % err = 100 x f out x dc err. 5. input and outputs lvpecl mode. 6. see figures 3-5 for output loads. ps(rms) mv(p-p)
lattice semiconductor ispclock5500 family data sheet 11 timing speci?ations skew matching programmable skew control control functions figure 6. reset and pro?e select timing symbol parameter conditions min. typ. max. units t skew output-output skew between any two identically con?ured and loaded outputs regardless of bank. 50 ps symbol parameter conditions min. typ. max. units t skrange skew control range 1 fine skew mode, f vco = 320 mhz 5.86 ns fine skew mode, f vco = 640 mhz 2.93 coarse skew mode, f vco = 320 mhz 11.72 coarse skew mode, f vco = 640 mhz 5.86 sk steps skew steps per range 16 t skstep skew step size 2 fine skew mode, f vco = 320 mhz 390 ps fine skew mode, f vco = 640 mhz 195 coarse skew mode, f vco = 320 mhz 780 coarse skew mode, f vco = 640 mhz 390 t skerr skew time accuracy 3 fine skew mode 30 ps coarse skew mode 50 1. skew control range is a function of vco frequency (f vco ). in ?e skew mode t skrange = 15/(8 x f vco ). in coarse skew mode t skrange = 15/(4 x f vco ). 2. skew step size is a function of vco frequency (f vco ). in ?e skew mode t skstep = 1/(8 x f vco ). in coarse skew mode t skstep = 1/(4 x f vco ). 3. only applicable to outputs with non-zero skew settings. symbol parameter conditions min. typ. max. units t dis/oe delay time, oex or oey to output disabled/ enabled ?020ns t dis/goe delay time, goe to output disabled/enabled 10 20 ns t susgate setup time, sgate to output clock start/ stop 3 cycles 1 t pll_rstw pll reset pulse width 15 ? t hps_rst hold time for reset past change in ps[0..1] 20 ns 1. output clock cycles for the particular output being controlled. t hps_rst t pll_rstw ps[0..1] reset
lattice semiconductor ispclock5500 family data sheet 12 timing speci?ations (cont.) boundary scan logic jtag interface and programming mode symbol parameter min. max. units t btcp tck (bscan test) clock cycle 40 ns t btch tck (bscan test) pulse width high 20 ns t btcl tck (bscan test) pulse width low 20 ns t btsu tck (bscan test) setup time 8 ns t bth tck (bscan test) hold time 10 ns t brf tck (bscan test) rise and fall rate 50 mv/ns t btco tap controller falling edge of clock to valid output 10 ns t btoz tap controller falling edge of clock to data output disable 10 ns t btvo tap controller falling edge of clock to data output enable 10 ns t bvtcpsu bscan test capture register setup time 8 ns t btcph bscan test capture register hold time 10 ns t btuco bscan test update register, falling edge of clock to valid output 25 ns t btuoz bscan test update register, falling edge of clock to output disable 25 ns t btuov bscan test update register, falling edge of clock to output enable 25 ns symbol parameter condition min. typ. max. units f max maximum tck clock frequency 25 mhz t ckh tck clock pulse width, high 20 ns t ckl tck clock pulse width, low 20 ns t ispen program enable delay time 15 ? t ispdis program disable delay time 30 ? t hvdis high voltage discharge time, program 30 s t hvdis high voltage discharge time, erase 200 ? t cen falling edge of tck to tdo active 15 ns t cdis falling edge of tck to tdo disable 15 ns t su1 setup time 8 ns t h hold time 10 ns t co falling edge of tck to valid output 15 ns t pwv verify pulse width 30 ? t pwp programming pulse width 20 ms t bew bulk erase pulse width 200 ms
lattice semiconductor ispclock5500 family data sheet 13 timing diagrams figure 7. erase (user erase or erase all) timing diagram figure 8. programming timing diagram figure 9. verify timing diagram figure 10. discharge timing diagram vih vil vih vil the clock (tck) must be able to run free with tms = vil the clock (tck) must be able to run free with tms = vil update-ir run-test/idle (erase) select-dr scan clock to shift-ir state and shift in the discharge instruction, then clock to the run-test/idle state run-test/idle (discharge) specified by the data sheet tms tck state t h t h t h t h t h t h t su1 t su1 t su1 t su1 t su1 t su1 t su2 t ckh t ckh t ckh t ckh t ckh t gkl t bew t gkl tms tck state vih vil vih vi l update-ir run-test/idle (program) select-dr scan clock to shift-ir state and shift in the next instruction, which will stop the discharge process update-ir the clock (tck) must be able to run free with tms = vil t su1 t su1 t su1 t su1 t su1 t h t h t h t h t h t ckl t pwp t ckh t ckh t ckh t ckh t ckl tms tck state vih vil vih vil update-ir run-test/idle (program) select-dr scan clock to shift-ir state and shift in the next instruction update-ir the clock (tck) must be able to run free with tms=vil t h t h t h t h t h t ckh t ckh t ckh t ckl t pwv t ckh t ckl t su1 t su1 t su1 t su1 t su1 tms tck state vih vil vih vil update-ir run-test/idle (erase or program) select-dr scan clock to shift-ir state and shift in the verify instruction, then clock to the run-test/idle state run-test/idle (verify) specified by the data sheet actual t h t h t h t h t h t h t su1 t ckh t hvdis (actual) t ckh t ckh t ckh t ckl t pwp or t bew t pwv t ckh t ckl t pwv t su1 t su1 t su1 t su1 t su1
lattice semiconductor ispclock5500 family data sheet 14 typical performance characteristics 0 0.2 0.4 0.6 0.8 1 1.2 300 0 3 6 9 12 15 320 400 480 560 640 400 500 600 700 i cco vs. output frequency (lvcmos 3.3v, normalized to 320mhz) cycle-cycle jitter vs. vco frequency v=4 typical cycle-cycle jitter vs. vco frequency pfd = 80 mhz period jitter vs. vco frequency v=4 i ccd vs. f vco (normalized to 640mhz) typical skew error vs. setting (skew mode = fine, f vco = 600mhz) 0 0.2 0.4 0.6 0.8 1 1.2 0 5 0 100 150 200 250 300 350 output frequency (mhz) skew setting # vco frequency (mhz) vco frequency (mhz) 320 300 350 400 450 500 550 700 600 650 400 480 560 640 vco frequency (mhz) f vco (mhz) normalized icco current normalized iccd current error vs. ideal (ps) period jitter (rms) ?ps cycle-cycle jitter (rms) ?ps -100 0 cycle-cycle jitter (rms) ?ps 0 20 40 60 80 100 120 140 5 10 15 20 25 30 -75 -50 -25 0 0 5 10 15 20 25 25 50 75 100 pfd = 20 mhz 20 mhz pfd = pfd = 80 mhz v = 16 v = 32 v = 8 v = 4 80 mhz pfd = 40 mhz 40 mhz *pfd = phase/frequency detector
lattice semiconductor ispclock5500 family data sheet 15 typical performance characteristics (cont.) detailed description pll subsystem the ispclock5500 provides an integrated phase-locked-loop (pll) which may be used to generate output clock signals at lower, higher, or the same frequency as a user-supplied input reference signal. the core functions of the pll are an edge-sensitive phase detector, a programmable loop ?ter, and a high-speed voltage-controlled oscilla- tor (vco). additionally, a set of programmable input, output and feedback dividers (m, n, v[1..5]) is provided to support the synthesis of different output frequencies. phase/frequency detector the ispclock5500 provides an edge-sensitive phase/frequency detector (pfd), which means that the device will function properly over a wide range of input clock reference duty cycles. it is only necessary that the input refer- ence clock meet speci?d minimum high and low times (t clockhi, t clocklo ) for it to properly recognized by the pfd. the pfds output is of a classical charge-pump type, outputting charge packets which are then integrated by the pll? loop ?ter. a lock-detection feature is also associated with the pfd. when the ispclock5500 is in a locked state, the lock output pin goes low. the lock detector has two operating modes; phase lock mode and frequency lock mode. in phase-lock mode, the lock signal is asserted if the phases of the reference and feedback signals match, whereas in frequency-lock mode the lock signal is asserted when the frequencies of the feedback and reference signals match. the option of which mode to use is programmable and may be set using pac-designer software (available from lattices web site at www .latticesemi.com ). in phase-lock mode the lock detector asserts the lock signal as soon as a lock condition is determined. in fre- quency-lock mode, however, the pll must be in a locked condition for a set number of phase detector cycles before the lock signal will be asserted. the number of cycles required before asserting the lock signal in fre- quency-lock mode can be set from 16 through 256, in increments of 16. the lock signal is generated in response to certain phase or frequency matches being detected at the input of the phase-frequency detector. therefore it is possible that the lock signal may be asserted before the pll has completely stabilized, and may change state while the pll is in the process of stabilizing. additionally, the output dividers are resynchronized in response to the frequency lock detector detecting a lock condition, even when the lock detector is set to phase mode. the frequency lock detector and phase lock detector are completely indepen- dent circuits. because the frequency lock detector requires a user-selectable number of cycles (16-256) to determine a lock con- dition, it is possible for the dividers to experience a resynchronization event a short time after a phase lock condi- tion is detected. this may result in an glitch or missing clock cycle on one or more of the outputs. for all of the typical period jitter vs. vco frequency pfd = 80 mhz vco frequency (mhz) 300 350 400 450 500 550 700 600 650 period jitter (rms) ?ps 120 100 80 60 40 20 0 v = 16 v = 32 v = 8 v = 4
lattice semiconductor ispclock5500 family data sheet 16 above reasons, it is recommended that when using phase-detect mode, the user wait a small amount of time (~25?) between the time the lock signal is ?st asserted and the time at which the output clock signals are assumed to be completely stable. when the lock condition is lost the lock signal will be de-asserted immediately in both phase-lock and frequency- lock detection modes. in frequency-lock mode, however, if the input reference signal is stopped, the lock output may continue to be asserted. in phase-lock mode, a loss of the input reference signal will always result in de-asser- tion of the lock output. loop filter a simpli?d schematic for the ispclock5500 loop ?ter is shown in figure 11. the ?ters capacitors are ?ed, and the response is controlled by setting the value of the phase-detectors output current sources and the value of the variable resistor. the phase detector output current has 14 possible settings, ranging from 3? to 55?, while the resistor may be set to any one of six values ranging from 2.3k to 9.3k. this provides a total of 84 unique i-r com- binations which may be selected. figure 11. ispclock5500 loop filter (simpli?d) because the selection of an optimal pll loop ?ter can be a daunting task, pac-designer offers a set of default ?- ter settings which will provide acceptable performance for most applications. the primary criterion for selecting one of these settings is the total division factor used in the feedback path. this factor is the ratio between the vco out- put frequency and the feedback v-divider output frequency which is the product of the n-divider and v feedback - divider (n x v feedback ). table 2 lists these default settings and conditions under which they should be used. table 2. pac-designer recommended loop filter settings the choice of loop ?ter parameters can have signi?ant effects on settling time, output jitter, and whether the pll will be fundamentally stable and be able to lock to an incoming signal. the values recommended in table 2 were n x v fbk i (?) r (k ? ) 2 to 8 5 2.3 10 7 2.3 12 to 14 9 2.3 16 11 2.3 18 to 20 13 2.3 22 15 2.3 24 to 26 17 2.3 28 19 2.3 30 21 2.3 32 to 64 22 2.3 to vco r c 2 c 1 i i phase detector from m-divider from n-divider
lattice semiconductor ispclock5500 family data sheet 17 chosen to provide maximum loop stability while still providing exceptional jitter performance. please note that when the skew mode is set to ?oarse? the effective value of nxv must be doubled. refer to the section titled ?oarse skew mode on page 30 for more details. the plls loop bandwidth is a function of both the divider con?uration and the loop ?ter settings. figure 12 shows the loop bandwidth as a function of the total feedback division ratio (n x v fbk ). for each nxv feedback divider point in this plot, the pll loop ?ter was set to the corresponding value recommended in table 2. the use of non-recom- mended loop ?ter settings may result in signi?antly different bandwidths for a given nxv divider setting. figure 12. pll loop bandwidth vs. feedback divider setting (nominal) vco the ispclock5500 provides an internal vco which provides an output frequency ranging from 320mhz to 640mhz. the vco is implemented using differential circuit design techniques which minimize the in?ence of power supply noise on measured output jitter. the vco is also used to generate skews as a function of the total vco period. using the vco as the basis for controlling output skew allows for highly precise and consistent skew generation, both from device-to-device, as well as channel-to-channel within the same device. m, n, and v dividers the ispclock5500 incorporates a set of programmable dividers which provide the ability to synthesize output fre- quencies differing from that of the reference clock input. the input, or m, divider prescales the input reference frequency, and can be programmed with integer values over the range of 1 to 32. to achieve low levels of output jitter, it is best to use the smallest m divider value possible. the feedback, or n, divider prescales the feedback frequency and like the m divider, can also be programmed with integer values ranging from 1 to 32. each one of the ?e output, or v, dividers can be independently programmed to provide even division ratios ranging from 2 to 64. when the pll is selected (pll_bypass=low) and locked, the output frequency of each v divider (f k ) may be cal- culated as: (1) pll loop bandwidth vs. feedback divider setting* (typical) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 016324864 n x v feedback division product *loop filter configured to recommended setting loop bandwidth (mhz) = f k f ref n x v fbk m x v k
lattice semiconductor ispclock5500 family data sheet 18 where f k is the frequency of v divider k f ref is the input reference frequency m and n are the input and feedback divider settings v fbk is the setting of the v divider used to close the pll feedback path v k is the setting of the v divider used to provide output k note that because the feedback may be taken from any v divider, v k and v fbk may refer to the same divider. because the vco has an operating frequency range spanning 320 mhz to 640 mhz, and the v dividers provide division ratios from 2 to 64, the ispclock5500 can generate output signals ranging from 5mhz to 320 mhz. for per- formance and stability reasons, however, there are several constraints which should be followed when selecting divider values: use the smallest feasible value for the m divider the output frequency from the m (and n) divider should be greater or equal to 10 mhz. the product of the n divider and the v divider used to close the plls feedback loop should be less than or equal to 64 (n x v fbk 64) output duty cycle the ispclock5500s output duty cycle varies as a function of the v divider used to generate that output. if the v- divider setting is either 2 or a multiple of 4, the nominal output duty cycle will be exactly 50%. all other v divider set- tings will result in non-50% output duty cycles. table 3 summarizes the nominal output duty cycle as a function of the v divider setting. note that if the output is inverted, the duty cycle will be equal to 100%-dc%, where dc% is the duty cycle indicated in the table. for example, with a v divider of 14, the non-inverted duty cycle from table 3 will be 43%. for an inverted output, the duty cycle will be 100%-43% or 57%. table 3. nominal output duty cycle vs. v-divider setting divider settings with 50% output duty cycle divider settings with non-50% output duty cycles v dc% v dc% 2 50 633 41040 81443 12 18 44 16 22 45 20 26 46 24 30 47 28 34 47 32 38 47 36 42 48 40 46 48 44 50 48 48 54 48 52 58 48 56 62 48 60 64
lattice semiconductor ispclock5500 family data sheet 19 figure 13 shows the relative timing for a v-divider as a function of its 32 possible divisor settings (2-64) as the pll locks. if two v-dividers are con?ured with the same divisor, their outputs will be synchronized. if these two v-divid- ers are fed to separate outputs, and the skew settings for these two outputs are identical, then the corresponding rising and falling edges for the two outputs will occur simultaneously. figure 13. ispclock5500 output divider timing relationships among various divisors if two v-dividers are con?ured with different divisors, however, their outputs may not necessarily have aligned edges, even in cases where one divisor is an integer multiple of the other (e.g. 6 and 12). in cases where the divi- sor is set to either 2 or a multiple of 4, the output duty cycle will be 50% (top set of waveforms in figure 13), and the rising edges (or falling edges) of outputs driven from different divisors may be aligned by inverting one or more of the outputs as shown in figure 14. /2 /4 /6 /8 /10 /12 /14 /16 /18 /20 /22 /24 /26 /28 /30 /32 /34 /36 /38 /40 /42 /44 /46 /48 /50 /52 /54 /56 /58 /60 /62 /64 0 102030405060 vco clock periods v-divider settings yielding 50% output duty cycle lock v-divider settings yielding non-50% output duty cycles
lattice semiconductor ispclock5500 family data sheet 20 figure 14. flipping polarity to edge align two outputs for v-divider combinations in which one or more of the v-dividers is con?ured to a value that is not divisible by 4 (e.g. 6), there exists the possibility that neither rising nor falling edges may align. for example, when v-divider val- ues of 6 and 12 are chosen, the two resulting outputs will have no edge alignment, as shown in figure 15. note that because the offset is 2 vco periods in this case, it is not possible to use the skew adjustment feature to force any of the edges into perfect alignment as the skew control units provide a maximum delay of 1.875 vco periods. figure 15. timing relationship between v-divider values of 6 and 12 pll_bypass mode the pll_bypass mode is provided so that input reference signals can be coupled through to the outputs without using the pll functions. when pll_bypass mode is enabled (pll_bypass=high), the output of the m divider is routed directly to the inputs of the v dividers. in pll_bypass mode, the nominal values of the v dividers are halved, so that they provide division ratios ranging from 1 to 32. the divide-by-1 setting, however, is invalid and will produce unde?ed results. the output frequency for a given v divider (f k ) will be determined by (2) please note that pll_bypass mode is provided primarily for testing purposes. when pll_bypass mode is enabled, features such as lock detect and skew generation are unavailable. reference inputs the ispclock5500 provides sets of con?urable, internally-terminated inputs for clock reference signals. in normal operation, the clock reference input (refa) is connected to the system clock from which the output signals are to be derived. the ispclock5510 provides one input signal pair for reference input, while the ispclock5520 provides two input pairs for reference signals. to select between reference inputs, the ispclock5520 provides a cmos-compatible dig- ital input called refsel. table 4 shows the behavior of this control input: table 4. refsel operation for ispclock5520 refsel selected input pair 0 refa+/- 1 refb+/- /8 /16 /8 /16 invert output polarity of /8 output trailing edges align leading edges align before after /6 / 12 edges never align = f k f ref m x v k
lattice semiconductor ispclock5500 family data sheet 21 clock reference inputs may be con?ured to interface to signals from the following logic families with little or no external support circuitry: lvttl (3.3v) lvcmos (1.8v, 2.5v, 3.3v) sstl2 sstl3 hstl lvds lvpecl (differential, 3.3v) each input also features internal programmable termination resistors, as shown in figure 16. figure 16. ispclock5500 clock reference input structure (refa+/- pair shown) the following usage guidelines are suggested for interfacing to supported logic families. lvttl (3.3v), lvcmos (1.8v, 2.5v, 3.3v) the receiver should be set to lvcmos or lvttl mode, and the input signal should be connected to the ? termi- nal of the input pair (e.g. refa+). the ? input terminal should be left ?ating. cmos transmission lines are gener- ally source terminated, so all termination resistors should be set to the open state. figure 17 shows the proper con?uration. please note that because switching thresholds are different for lvcmos running at 1.8v, there is a separate con?uration setting for this particular standard. r t r t refa- refa+ refvtt to internal logic single-ended ispclock5500 receiver differential receiver
lattice semiconductor ispclock5500 family data sheet 22 figure 17. lvcmos/lvttl input receiver con?uration hstl, sstl2, sstl3 the receiver should be set to hstl/sstl mode, and the input signal should be fed into the ? terminal of the input pair. the ? input terminal should be tied to the appropriate v ref value, and the refvtt terminal should be tied to a v tt termination supply. the positive inputs terminating resistor should be engaged and set to 50 ? . figure 18 shows an appropriate con?uration. refer to the ?ecommended operating conditions - supported logic stan- dards table in this data sheet for suitable values of v ref and v tt. one important point to note is that the termination supplies must have low impedance and be able to both source and sink current without experiencing ?ctuations. these requirements generally preclude the use of a resistive divider network, which has an impedance comparable to the resistors used, or of commodity-type linear voltage regulators, which can only source current. the best way to develop the necessary termination voltages is with a regulator speci?ally designed for this purpose. because sstl and hstl logic is commonly used for high-perfor- mance memory busses, a suitable termination voltage supply is often already available in the system. figure 18. sstl2, sstl3, hstl receiver con?uration r t open refa- refa+ refvtt single-ended receiver no connect no connect signal in ispclock5500 50 closed refa- refa+ refvtt vtt differential receiver vref in signal in ispclock5500 open
lattice semiconductor ispclock5500 family data sheet 23 differential hstl and sstl hstl and sstl are sometimes used in a differential form, especially for distributing clocks in high-speed memory systems. figure 19 shows how ispclock5500 reference input should be con?ured for accepting these standards. the major difference between the differential and single-ended forms of these logic standards is that in the differen- tial cases, the refa- input is used as a signal input, not a reference level, and that both terminating resistors are engaged and set to 50 ? . figure 19. differential hstl/sstl receiver con?uration lvds/differential lvpecl the receiver should be set to lvds or lvpecl mode as required and both termination resistors should be engaged and set to 50 ? . the refvtt pin, however, should be left unconnected. this creates a ?ating 100 ? dif- ferential termination resistance across the input terminals. the lvds termination con?uration is shown in figure 20. figure 20. lvds input receiver con?uration 50 closed refa- refa+ refvtt differential receiver +signal in ispclock5500 closed -signal in 50 vtt 50 closed refa- refa+ refvtt differential receiver +signal in closed -signal in 50 no connect lv d s driver ispclock5500
lattice semiconductor ispclock5500 family data sheet 24 note that while a ?ating 100 ? resistor forms a complete termination for an lvds signal line, additional circuitry may be required to satisfactorily terminate a differential lvpecl signal. this is because a true bipolar lvpecl out- put driver typically requires an external dc ?ull-down path to a v term termination voltage (typically vcc-2v) to properly bias its open emitter output stage. when interfacing to an lvpecl input signal, the ispclock5500s inter- nal termination resistors should not be used for this pull-down function, as they may be damaged from excessive current. the pull-down should be implemented with external resistors placed close to the lvpecl driver (figure 21) figure 21. lvpecl input receiver con?uration please note that while the above discussions specify using 50 ? termination impedances, the actual impedance required to properly terminate the transmission line and maintain good signal integrity may vary from this ideal. the actual impedance required will be a function of the driver used to generate the signal and the transmission medium used (pcb traces, connectors and cabling). the ispclock5500s ability to adjust input impedance over a range of 40 ? to 70 ? allows the user to adapt his circuit to non-ideal behaviors from the rest of the system without having to swap out components. output drivers the ispclock5500 provide banks of con?urable, internally-terminated high-speed dual-output line drivers. the ispclock5510 provides ?e driver banks, while the ispclock5520 provides ten. each of these driver banks may be con?ured to provide either a single differential output signal, or a pair of single-ended output signals. programma- ble internal source-series termination allows the ispclock5500 to be matched to transmission lines with imped- ances ranging from 40 to 70 ohms. the outputs may be independently enabled or disabled, either from e 2 cmos con?uration or by external control lines. additionally, each can be independently programmed to provide a ?ed amount of signal delay or skew, allowing the user to compensate for the effects of unequal pcb trace lengths or loading effects. figure 22 shows a block diagram of a typical ispclock5500 output driver bank and associated skew control. because of the high edge rates which can be generated by the ispclock5500s clock output drivers, the vcco power supply pin for each output bank should be individually bypassed. low esr capacitors with values ranging from 0.01 to 0.1 ? may be used for this purpose. each bypass capacitor should be placed as close to its respec- tive output bank power pins (vcco and gndo) pins as is possible to minimize interconnect length and associated parasitic inductances. 50 closed refa- refa+ refvtt differential receiver +signal in closed -signal in 50 no connect lvpecl driver ispclock5500 r pd r pd v term
lattice semiconductor ispclock5500 family data sheet 25 in the case where an output bank is unused, the associated vcco pin may be either left ?ating or tied to ground to reduce quiescent power consumption. we recommend, however, that all unused vcco pins be tied to ground where possible. all gndd pins must be tied to ground, regardless of whether or not the associated bank is used. figure 22. ispclock5500 output driver and skew control each of the ispclock5500s output driver banks can be con?ured to support the following logic outputs: lvttl lvcmos (1.8v, 2.5v, 3.3v) sstl2 sstl3 hstl lvds differential lvpecl (3.3v) to provide lvttl, lvcmos, sstl2, sstl3, and hstl outputs, the cmos output drivers in each bank are enabled. these circuits provide logic outputs which swing from ground to the vcco supply rail. the choice of vcco to be supplied to a given bank is determined by the logic standard to which that bank is con?ured. because each pair of outputs has its own vcco supply pin, each bank can be independently con?ured to support a differ- ent logic standard. note that the two outputs associated with a bank must necessarily be con?ured to the same logic standard. the source impedance of each of the two outputs in each bank may be independently set over a range of 40 ? to 70 ? in 5 ? steps. a low impedance option ( 20 ? ) is also provided for cases where low source ter- mination is desired on a given output, such as when using hstl output mode. control of output slew rate is also provided in lvttl, lvcmos, sstl2, sstl3, and hstl output modes. four output slew-rate settings are provided, as speci?d in the ?utput rise times and ?utput fall times tables in this data sheet. to provide lvds and differential lvpecl outputs, a separate driver is used which provides the correct lvds or lvpecl logic levels when operating from a 3.3v vcco. because both lvds and differential lvpecl transmission lines are normally terminated with a single 100 ? resistor between the ? and ? signal lines at the far end, the oe control from v-dividers skew adjust skew adjust bankxa bankxb single-ended ? output driver single-ended ? output driver differential (pecl/lvds) driver oe control oe control
lattice semiconductor ispclock5500 family data sheet 26 ispclock5500s internal termination resistors are not available in these modes. also note that output slew-rate con- trol is not available in lvds or lvpecl mode, and that these drivers always operate at a ?ed slew-rate. polarity control (true/inverted) is available for all output drivers. in the case of single-ended output standards, the polarity of each of the two output signals from each bank may be controlled independently. in the case of differen- tial output standards, the polarity of the differential pair may be selected. suggested usage figure 23 shows a typical con?uration for the ispclock5500s output driver when con?ured to drive an lvttl or lvcmos load. the ispclock5500s output impedance should be set to match the characteristic impedance of the transmission line being driven. the far end of the transmission line should be left open, with no termination resis- tors. figure 23. con?uration for lvttl/lvcmos output modes figure 24 shows a typical con?uration for the ispclock5500s output driver when con?ured to drive sstl2, sstl3, or hstl loads. the ispclock5500s output impedance should be set to 40 ? for driving sstl2 or sstl3 loads and to the 20 ? setting for driving hstl. the far end of the transmission line must be terminated to an appropriate vtt voltage through a 50 ? resistor. figure 24. con?uration for sstl2, sstl3, and hstl output modes while supporting single-ended hstl and sstl outputs, the ispclock5500 does not support differential hstl or sstl. although complementary hstl and sstl signals may be generated by using both an inverted output and a non-inverted output similarly con?ured, the resulting signal pair may not meet the jedec differential hstl speci- ?ations for common mode voltage or crossover voltage. figure 25 shows a typical con?uration for the ispclock5500s output driver when con?ured to drive lvds or dif- ferential lvpecl loads. the ispclock5500s output impedance is disengaged when the driver is set to lvds or zo ro = zo ispclock5500 lvcmos/lvttl mode lvcmos/lvttl receiver zo=50 ro : 40 ? (sstl) 20 ? (hstl) ispclock5500 sstl/hstl mode sstl/hstl receiver vtt vref rt=50
lattice semiconductor ispclock5500 family data sheet 27 lvpecl mode. the far end of the transmission line must be terminated with a 100 ? resistor across the two signal lines. figure 25. con?uration for lvds and lvpecl output modes note that when in lvpecl output mode, the ispclock5500s output driver provides an internal pull-down, unlike a typical bipolar lvpecl driver. for this reason no external pull-down resistors are necessary and the driver may be terminated with a single 100 ? resistor across the signal lines. for proper operation, pull-down resistors should not be used with the ispclock5500s lvpecl output mode. thermal management in applications where a majority of the ispclock5510 or ispclock5520s outputs are active and operating at or near maximum output frequency (320 mhz), package thermal limitations may need to be considered to ensure a suc- cessful design. thermal characteristics of the packages employed by lattice semiconductor may be found in the document thermal management which may be obtained at www .latticesemi.com . the maximum current consumption of the digital and analog core circuitry is approximately 157ma worst case (i ccd + i cca ), and each of the output banks may draw up to 35ma worst case (lvcmos 3.3v, cl=18pf, f out =320 mhz, both outputs in each bank enabled). this results in a total device dissipation: p dmax = 3.3v x (10 x 35ma + 157ma) = 1.67w (3) with a maximum recommended operating junction temperature (t jop ) of 115? for an industrial grade device, the maximum allowable ambient temperature (t amax ) can be estimated as t amax = t jop - pd max x ja = 115? - 1.67w x 35?/w = 56? (4) where ja = 35 ?/w for the 100 tqfp package and ja = 48 ?/w for the 48 tqfp package in still air. the above analysis represents the worst-case scenario. signi?ant improvement in maximum ambient operating temperature can be realized with additional cooling. providing a 200 lfm (linear feet per minute) air?w reduces ja to 29?/w, which results in a maximum ambient operating temperature of 66?. in practice, however, the absolute worst-case situation will be relatively rare, as not all outputs may be running at maximum output frequency in a given application. additionally, if the internal vco is operating at less than its max- imum frequency (640mhz), it requires less current on the vccd pin. in these situations, one can estimate the effective i cco for each bank and the effective i ccd for the digital core functions based on output frequency and vco frequency. normalized curves relating current to operating frequency for these parameters may be found in the typical performance characteristics section. while it is possible to perform detailed calculations to estimate the maximum ambient operating temperature from operating conditions, some simpler rule-of-thumb guidance can also be obtained through the derating curves shown in figure 26. the curves in figure 26a show the maximum ambient operating temperature permitted when operating a given number of output banks at the maximum output frequency (320mhz). note that it is assumed that both outputs in each bank are active. zo=50 ispclock5500 lvds/lvpecl mode lvds/pecl receiver rt=100 zo=50
lattice semiconductor ispclock5500 family data sheet 28 figure 26. maximum ambient temperature vs. number of active output banks figure 26b shows another derating curve, derived under the assumption that the output frequency is 100mhz. for many applications, 100mhz outputs will be a more realistic scenario. comparing the maximum temperature limits of figure 26b with figure 26a, one can see that signi?antly higher operating temperatures are possible in lvc- mos 3.3v output mode with more outputs at 100mhz than at 320mhz. the examples above described examples using lvcmos 3.3v logic, which represents the maximum power dissi- pation case at higher frequencies. for optimal operation at very high frequencies (> 150 mhz) lvds will often be the best choice from a signal integrity standpoint. for lvds-con?ured outputs, the maximum icco current con- sumption per bank is low enough that both the ispclock5510 and ispclock5520 can operate all outputs at maxi- mum frequency over their complete rated temperature range, as shown in figure 26c. note that because of variations in circuit board mounting, construction, and layout, as well as convective and forced air?w present in a given design, actual die operating temperature is subject to considerable variation from that which may be theoretically predicted from package characteristics and device power dissipation. output enable controls the ispclock5500 family provides the user with several options for enabling and disabling output pins, as well as suspending the output clock. in addition to providing the user with the ability to reduce the devices power con- sumption by turning off unused drivers, these features can also be used for functional testing purposes. the follow- ing inputs pins are used for output enable functions: temperature derating curves (outputs lvcmos 3.3v, f out =320 mhz) temperature derating curves (outputs lvcmos 3.3v, f out =100 mhz) temperature derating curves (outputs lvds, f out =320 mhz) 40 50 60 70 80 90 40 50 60 70 80 90 40 50 60 70 80 90 0246810 maximum ambient temp. c maximum ambient temp. c 5520 commercial 5520 industrial 5510 commericial 5510 industrial # active output banks (a) 0246810 # active output banks (b) 0246810 # active output banks (c) maximum ambient temp. ?c
lattice semiconductor ispclock5500 family data sheet 29 goe ?global output enable oex , oey ?secondary output enable controls sgate ?synchronous output control additionally, internal e 2 cmos con?uration bits are provided for the purpose of modifying the effects of these external control pins. when goe is high, all output drivers are forced into a high-z state, regardless of any internal con?uration. when goe is low, the output drivers may also be enabled or disabled on an individual basis, and optionally controlled by the oex and oey pins. internal e 2 cmos con?uration is used to establish whether the output driver is always enabled (when goe pin is low), never enabled (permanently off), or selectively enabled by the state of either oex or oey . bringing goe high will also disable the internal feedback driver and will result in a loss of lock. synchronous output gating is provided by ispclock5500 devices through the use of the sgate pin. the sgate pin does not disable the output driver, but merely forces the output to either a high or low state, depending on the out- put drivers polarity setting. if the output driver polarity is true, the output will be forced low when sgate is brought low, while if it is inverted, the output will be forced high. a primary feature of the sgate function is that the clock output is enabled and disabled synchronous to the selected internal clock source. this prevents the gen- eration of partial, ?unt? output clock pulses, which would otherwise occur with simple combinatorial gating schemes. the sgate is available to all clock outputs and is selectable on a bank-by-bank basis. table 5 shows the behavior of the outputs for various combinations of the output enables, sgate input, and e 2 cmos con?uration. table 5. clock output enable functions table 6. sgate function skew control units each of the ispclock5500s clock outputs is supported by a skew control unit which allows the user to insert an indi- vidually programmable delay into each output signal. this feature is useful when it is necessary to de-skew clock signals to compensate for physical length variations among different pcb clock paths. unlike the skew adjustment features provided in many competing products, the ispclock5500s skew adjustment feature provides exact and repeatable delays which exhibit extremely low channel-to-channel and device-to-device variation. this is achieved by deriving all skew timing from the vco, which results in the skew increment being a lin- ear function of the vco period. for this reason, skews are de?ed in terms of ?ime units (tus), which may be pro- goe oex oey e 2 con?uration output x x x always off high-z 0 x x always on clock out 0 0 x enable on oex clock out 0 1 x enable on oex high-z 0 x 0 enable on oey clock out 0 x 1 enable on oey high-z 1 x x n/a high-z sgate bank controlled by sgate? output polarity output x no true clock x no inverted inverted clock 0 yes true low 0 yes inverted high 1 yes true clock 1 yes inverted inverted clock
lattice semiconductor ispclock5500 family data sheet 30 grammed by the user over a range of 0 to 15. the ispclock5500 family also supports both ne and ?oarse skew modes. in ?e skew mode, the unit skew ranges from 195ps to 390 ps, while in the coarse skew mode unit skew varies from 390ps to 780ps. the value of one tu may be calculated from the vco frequency (f vco ) by using the fol- lowing expressions: (5) when an output driver is programmed to support a differential output mode, a single skew setting is applied to both the bankxa+ and bankxb- signals. when the output driver is con?ured to support a single-ended output stan- dard, each of the two single-ended outputs may be assigned independent skews. by using the internal feedback path, and programming a skew into the feedback skew control, it is possible to implement negative timing skews, in which the clock edge of interest appears at the ispclock5500s output before the corresponding edge is presented at the reference input. when the feedback skew unit is used in this way, the resulting negative skew is added to whatever skew is speci?d for each output. for example, if the feedback skew is set to 6tu, bank1s skew is 8tu and bank2s skew is 3tu, then bank1s effective output skew will be 2tu (8tu-6tu), while bank2s effective skew will be -3tu (3tu-6tu). this negative skew will manifest itself as bank2s outputs appearing to lead the input reference clock, appearing as a negative propagation delay. please note that the skew control units are only usable when the pll is selected. in pll bypass mode (pll_bypass=1), output skew settings will be ineffective and all outputs will exhibit skew consistent with the devices propagation delay and the individual delays inherent in the output drivers consistent with the logic stan- dard selected. coarse skew mode the ispclock5500 family provides the user with the option of obtaining longer skew delays at the cost of reduced time resolution through the use of coarse skew mode. coarse skew mode provides tu values ranging from 390ps (f vco = 640mhz) to 780ps (f vco = 320mhz), which is twice as long as those provided in ?e skew mode. when coarse skew mode is selected, an additional divide-by-2 stage is effectively inserted between the vco and the v- divider bank, as shown in figure 27. when assigning divider settings in coarse skew mode, one must account for this additional divide-by-two so that the vco still operates within its speci?d range (320-640mhz). figure 27. additional factor-of-2 division in coarse mode when one moves from ?e skew mode to coarse skew mode with a given divider con?uration, the vco frequency will attempt to double to compensate for the additional divide-by-2 stage. because the f vco range is not increased, however, one must modify the feedback path v-divider settings to bring f vco back into its speci?d operating range (320mhz to 640mhz). this can be accomplished by dividing all v-divider settings by two. all output frequencies will remain unchanged from what they were in ?e mode. one drawback of moving from ?e skew mode into coarse skew mode is that it may not be possible to maintain consistent output frequencies, as only those v-divider settings which are multiples of four (in ?e mode) may be divided by two. for example, a v-divider setting of 24 will divide down to 12, which is also a legal v-divider setting, whereas an initial setting of 26 would divide down to 13, which is not a valid setting. = tu for fine skew mode, 1 8f vco = tu for coarse skew mode, 1 4f vco vco 2 v-dividers fine mode fout coarse mode
lattice semiconductor ispclock5500 family data sheet 31 when one moves from coarse skew mode to ?e skew mode, the extra divide-by-two factor is removed from between the vco and the v-divider bank, halving the vcos effective operating frequency. to compensate for this change, all of the v-dividers must be doubled to move the vco back into its speci?d operating range and maintain consistent output frequencies. the only situation in which this may be a problem is when a v-divider initially in coarse mode has a value greater than 32, as the corresponding ?e skew mode setting would be greater than 64, which is not supported. skew matching and accuracy understanding the various factors which relate to output skew is essential for realizing optimal skew performance in the ispclock5500 family of devices. in the case where two outputs are identically con?ured, and driving identical loads, the maximum skew is de?ed by t skew, which is speci?d as a maximum of 50ps. in figure 28 the bank1a and bank2a outputs show the skew error between two matched outputs. figure 28. skew matching error sources one can also program a user-de?ed skew between two outputs using the skew control units. because the pro- grammable skew is derived from the vco frequency, as described in the previous section, the absolute skew is very accurate. the typical error for any non-zero skew setting is given by the t skerr speci?ation. for example, if one is in ?e skew mode with a vco frequency of 500mhz, and selects a skew of 8tu, the realized skew will be 2ns, which will typically be accurate to within +/-30 ps. an example of error vs. skew setting can be found in the chart ?ypical skew error vs. setting in the typical performance characteristics section. note that this parameter adds to output-to-output skew error only if the two outputs have different skew settings. the bank1a and bank3a outputs in figure 28 show how the various sources of skew error stack up in this case. note that if two or more out- puts are programmed to the same skew setting, then the contribution of the t skerr skew error term does not apply. when outputs are con?ured or loaded differently, this also has an effect on skew matching. if an output is set to support a different logic type, this can be accounted for by using the t ioo output adders speci?d in the table ?witching characteristics? that table speci?s the additional skew added to an output using lvpecl as a base- line. for instance, if one output is speci?d as lvttl (t ioo = 0.1ns), and another output is speci?d as lvpecl (t ioo = 0ns), then one could expect 0.1ns of additional skew between the two outputs. this timing relationship is shown in figure 29a. +/- t skew 2ns +/- (t skew ) +/- (t skerr ) bank1a (skew setting = 0) bank2a (skew setting=0) bank3a (skew setting = 2ns)
lattice semiconductor ispclock5500 family data sheet 32 figure 29. output timing adders for logic type (a) and output slew rate (b) similarly, when one changes the slew rate of an output, the output slew rate adders (t ios ) can be used to predict the resulting skew. in this case, the fastest slew setting (1) is used as the baseline against which other slews are measured. for example, in the case of outputs con?ured to the same logic type (e.g. lvcmos 1.8v), if one output is set to the fastest slew rate (1, t ios = 0ps), and another set to slew rate 3 (t ios = 660ps), then one could expect 660ps of skew between the two outputs, as shown in figure 29b. other features pro?e select the ispclock5500 stores all internal con?uration data in on-board e 2 cmos memory. up to four independent con- ?uration pro?es may be stored in each device. the choice of which con?uration pro?e is to be active is speci?d thought the pro?e select inputs ps0 and ps1, as shown in table 7. table 7. pro?e select function each pro?e controls the following internal con?uration items: m divider setting ? n divider setting ? v divider settings ? pll loop ?ter settings ? output skew settings ? internal feedback delay compensation the following settings are independent of the selection of active pro?e and will apply regardless of which pro?e is selected: input logic con?uration ?logic family ?input impedance output bank logic con?uration ?logic family ?v-divider signal source ?enable/sgate control options ?output impedance ?slew rate ps1 ps0 active pro?e 0 0 pro?e 0 0 1 pro?e 1 1 0 pro?e 2 1 1 pro?e 3 lvpecl output (t ios = 0) lvttl output (t ios = 0.1ns) 0.1ns (a) lvcmos output (slew rate=1) lvcmos output (slew rate=3) 660ps (b)
lattice semiconductor ispclock5500 family data sheet 33 ?signal inversion v-divider to be used as feedback source internal feedback delay compensation fine/coarse skew mode selection ues string if any of the above items are modi?d, the change will apply across all pro?es. in some cases this may cause unanticipated behavior. if multiple pro?es are used in a design, the suitability of the pro?e independent settings must be considered with respect to each of the individual pro?es. when a pro?e is changed by modifying the values of the ps0 and ps1 inputs, it is necessary to assert a reset signal to the ispclock5500 to restart the pll and resynchronize all the internal dividers. reset and power-up functions to ensure proper pll startup and synchronization of outputs, the ispclock5500 provides both internally generated and user-controllable external reset signals. an internal reset is generated whenever the device is powered up. an external reset may be applied by asserting a logic high at the reset pin. please note that the reset pin does not have an internal pull-up or pull-down resistor associated with it and should be tied low if not used. asserting reset resets all internal dividers, and will cause the pll to lose lock. on losing lock, the vco frequency will begin dropping. the length of time required to regain lock is related to the length of time for which reset was asserted. output phase relationships among the outputs may not be valid until the ispclock5500 asserts its lock output. when the ispclock5500 begins operating from initial power-on, the vco starts running at a very low frequency (<100 mhz) which gradually increases as it approaches a locked condition. to prevent invalid outputs from being applied to the rest of the system, it is recommended that either the sgate, oex , or oey pins be used to control the outputs based on the status of the lock pin. holding the sgate pin low during power-up will result in the bank outputs being asserted high or low (depending on inversion status) until sgate is brought high. assert- ing oex or oey high will result in the bank outputs being held in a high-impedance state until the oex or oey pin is pulled low. one should not use the goe pin to control the outputs in anticipation of lock status, as holding goe high also disables internal feedback and will prevent the device from ever achieving lock. software-based design environment designers can con?ure the ispclock5500 using lattices pac-designer software, an easy to use, microsoft windows compatible program. circuit designs are entered graphically and then veri?d, all within the pac-designer environ- ment. full device programming is supported using pc parallel port i/o operations and a download cable connected to the serial programming interface pins of the ispclock5500. a library of con?urations is included with basic solutions and examples of advanced circuit techniques are available on the lattice web site at www .latticesemi.com . in addi- tion, comprehensive on-line and printed documentation is provided that covers all aspects of pac-designer operation. the pac-designer schematic window, shown in figure 30 provides access to all con?urable ispclock5500 elements via its graphical user interface. all analog input and output pins are represented. static or non-con?urable pins such as power, ground and the serial digital interface are omitted for clarity. any element in the schematic window can be accessed via mouse operations as well as menu commands. when completed, con?urations can be saved and downloaded to devices.
lattice semiconductor ispclock5500 family data sheet 34 figure 30. pac-designer design entry screen (ispclock5520) in-system programming the ispclock5500 is an in-system programmable (isp) device. this is accomplished by integrating all e 2 cmos con?uration control logic on-chip. programming is performed through a 4-wire, ieee 1149.1 compliant serial jtag interface at normal logic levels. once a device is programmed, all con?uration information is stored on-chip, in non-volatile e 2 cmos memory cells. the speci?s of the ieee 1149.1 serial interface and all ispclock5500 instruc- tions are described in the jtag interface section of this data sheet. user electronic signature a user electronic signature (ues) feature is included in the e 2 cmos memory of the ispclock5500. this consists of 32 bits that can be con?ured by the user to store unique data such as id codes, revision numbers or inventory control data. the speci?s this feature are discussed in the ieee 1149.1 serial interface section of this data sheet. electronic security an electronic security ?use (esf) bit is provided in every ispclock5500 device to prevent unauthorized readout of the e 2 cmos con?uration bit patterns. once programmed, this cell prevents further access to the functional user bits in the device. this cell can only be erased by reprogramming the device, so the original con?uration can not be examined once programmed. usage of this feature is optional. the speci?s of this feature are discussed in the ieee 1149.1 serial interface section of this data sheet. production programming support once a ?al con?uration is determined, an ascii format jedec ?e can be created using the pac-designer soft- ware. devices can then be ordered through the usual supply channels with the users speci? con?uration already preloaded into the devices. by virtue of its standard interface, compatibility is maintained with existing production programming equipment, giving customers a wide degree of freedom and ?xibility in production planning. evaluation fixture included in the basic ispclock5500 design kit is an engineering prototype board that can be connected to the par- allel port of a pc using a lattice ispdownload cable. it demonstrates proper layout techniques for the ispclock5500 and can be used in real time to check circuit operation as part of the design process. input and out- put connections (sma connectors for all rf signals) are provided to aid in the evaluation of the ispclock5500 for a given application. (figure 31). part number description pac-systemclk5520 complete system kit, evaluation board, ispdownload cable and software. PACCLK5520-EV evaluation board only, with components, fully assembled.
lattice semiconductor ispclock5500 family data sheet 35 figure 31. download from a pc ispdownload cable (6') 4 other system circuitry ispclock5500 device pac-designer software
lattice semiconductor ispclock5500 family data sheet 36 ieee standard 1149.1 interface (jtag) serial port programming interface communication with the ispclock5500 is facilitated via an ieee 1149.1 test access port (tap). it is used by the ispclock5500 both as a serial programming interface, and for boundary scan test purposes. a brief description of the ispclock5500 jtag interface follows. for complete details of the reference speci?ation, refer to the publication, standard test access port and boundary-scan architecture, ieee std. 1149.1-1990 (which now includes ieee std. 1149.1a-1993). overview an ieee 1149.1 test access port (tap) provides the control interface for serially accessing the digital i/o of the ispclock5500. the tap controller is a state machine driven with mode and clock inputs. given in the correct sequence, instructions are shifted into an instruction register which then determines subsequent data input, data output, and related operations. device programming is performed by addressing the con?uration register, shifting data in, and then executing a program con?uration instruction, after which the data is transferred to internal e 2 cmos cells. it is these non-volatile cells that store the con?uration or the ispclock5500. a set of instructions are de?ed that access all data registers and perform other internal control operations. for compatibility between compliant devices, two data registers are mandated by the ieee 1149.1 speci?ation. others are functionally spec- i?d, but inclusion is strictly optional. finally, there are provisions for optional data registers de?ed by the manu- facturer. the two required registers are the bypass and boundary-scan registers. figure 32 shows how the instruction and various data registers are organized in an ispclock5500. figure 32. ispclock5500 tap registers tap controller speci?s the tap is controlled by the test clock (tck) and test mode select (tms) inputs. these inputs determine whether an instruction register or data register operation is performed. driven by the tck input, the tap consists of a small 16-state controller design. in a given state, the controller responds according to the level on the tms input as shown in figure 33. test data in (tdi) and tms are latched on the rising edge of tck, with test data out (tdo) becoming valid on the falling edge of tck. there are six steady states within the controller: test-logic-reset, run- address register (10 bits) e 2 cmos non-volatile memory ues register (32 bits) idcode register (32 bits) bypass register (1 bit) instruction register (8 bits) test access port (tap) logic output latch tdi tck tms tdo b-scan register (56 bits) multiplexer data register (90 bits)
lattice semiconductor ispclock5500 family data sheet 37 test/idle, shift-data-register, pause-data-register, shift-instruction-register and pause-instruction-register. but there is only one steady state for the condition when tms is set high: the test-logic-reset state. this allows a reset of the test logic within ?e tcks or less by keeping the tms input high. test-logic-reset is the power-on default state. figure 33. tap states when the correct logic sequence is applied to the tms and tck inputs, the tap will exit the test-logic-reset state and move to the desired state. the next state after test-logic-reset is run-test/idle. until a data or instruction shift is performed, no action will occur in run-test/idle (steady state = idle). after run-test/idle, either a data or instruc- tion shift is performed. the states of the data and instruction register blocks are identical to each other differing only in their entry points. when either block is entered, the ?st action is a capture operation. for the data regis- ters, the capture-dr state is very simple: it captures (parallel loads) data onto the selected serial data path (previ- ously chosen with the appropriate instruction). for the instruction register, the capture-ir state will always load the idcode instruction. it will always enable the id register for readout if no other instruction is loaded prior to a shift-dr operation. this, in conjunction with mandated bit codes, allows a ?lind interrogation of any device in a compliant ieee 1149.1 serial chain. from the capture state, the tap transitions to either the shift or exit1 state. normally the shift state follows the capture state so that test data or status information can be shifted out or new data shifted in. following the shift state, the tap either returns to the run-test/idle state via the exit1 and update states or enters the pause state via exit1. the pause state is used to temporarily suspend the shifting of data through either the data or instruction register while an external operation is performed. from the pause state, shifting can resume by reentering the shift state via the exit2 state or be terminated by entering the run-test/idle state via the exit2 and update states. if the proper instruction is shifted in during a shift-ir operation, the next entry into run-test/idle initiates the test mode (steady state = test). this is when the device is actually programmed, erased or veri?d. all other instructions are executed in the update state. test instructions like data registers, the ieee 1149.1 standard also mandates the inclusion of certain instructions. it outlines the function of three required and six optional instructions. any additional instructions are left exclusively for the manu- test-logic-rst run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 00 0 0 00 11 00 00 11 11 00 11 00 11 11 11 1 0 note: the value shown adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck.
lattice semiconductor ispclock5500 family data sheet 38 facturer to determine. the instruction word length is not mandated other than to be a minimum of two bits, with only the bypass and extest instruction code patterns being speci?ally called out (all ones and all zeroes respec- tively). the ispclock5000 contains the required minimum instruction set as well as one from the optional instruction set. in addition, there are several proprietary instructions that allow the device to be con?ured and veri?d. for ispclock5000, the instruction word length is eight bits. all ispclock5000 instructions available to users are shown in table 8. the following table lists the instructions supported by the ispclock5500 jtag test access port (tap) controller: table 8. ispclock5500 tap instruction table bypass is one of the three required instructions. it selects the bypass register to be connected between tdi and tdo and allows serial data to be transferred through the device without affecting the operation of the ispclock5500. the ieee 1149.1 standard de?es the bit code of this instruction to be all ones (111111). the required sample/preload instruction dictates the boundary-scan register be connected between tdi and tdo. the bit code for this instruction is de?ed by lattice as shown in table 8. the extest (external test) instruction is required and will place the device into an external boundary test mode while also enabling the boundary scan register to be connected between tdi and tdo. the bit code of this instruc- tion is de?ed by the 1149.1 standard to be all zeros (000000). the optional idcode (identi?ation code) instruction is incorporated in the ispclock5500 and leaves it in its func- tional mode when executed. it selects the device identi?ation register to be connected between tdi and tdo. the identi?ation register is a 32-bit shift register containing information regarding the ic manufacturer, device instruction code description extest 0000 0000 external test. address_shift 0000 0001 address register (10 bits) data_shift 0000 0010 address column data register (89 bits) bulk_erase 0000 0011 bulk erase program 0000 0111 program column data register to e 2 program_security 0000 1001 program electronic security fuse verify 0000 1010 verify column discharge 0001 0100 fast vpp discharge program_enable 0001 0101 enable program mode idcode 0001 0110 address manufacturer id code register (32 bits) usercode 0001 0111 read ues data from e 2 and addresses ues register (32 bits) program_usercode 0001 1010 program ues register into e 2 program_disable 0001 1110 disable program mode highz 0001 1000 force all outputs to high-z state sample/preload 0001 1100 capture current state of pins to boundary scan register clamp 0010 0000 drive i/os with boundary scan register user_logic_reset 0010 0010 resets user logic intest 0010 1100 performs in-circuit functional testing of device. erase done 0010 0100 erases the ?one bit only prog_incr 0010 0111 program column data register to e 2 and auto-increment address register verify_incr 0010 1010 load column data register from e 2 and auto-increment address register program_done 0010 1111 programs the ?one bit noop 0011 0000 functions similarly to clamp instruction bypass 1xxx xxxx bypass - connect tdo to tdi
lattice semiconductor ispclock5500 family data sheet 39 type and version code (figure 34). access to the identi?ation register is immediately available, via a tap data scan operation, after power-up of the device, or by issuing a test-logic-reset instruction. the bit code for this instruction is de?ed by lattice as shown in table 8. figure 34. ispclock5500 family id codes in addition to the four instructions described above, there are 20 unique instructions speci?d by lattice for the ispclock5520. these instructions are primarily used to interface to the various user registers and the e 2 cmos non- volatile memory. additional instructions are used to control or monitor other features of the device, including bound- ary scan operations. a brief description of each unique instruction is provided in detail below, and the bit codes are found in table 8. program_enable ?this instruction enables the ispclock5500s programming mode. program_disable ?this instruction disables the ispclock5500s programming mode. bulk_erase ?this instruction will erase all e 2 cmos bits in the device, including the ues data and electronic security fuse (esf). a bulk erase instruction must be issued before reprogramming a device. the device must already be in programming mode for this instruction to execute. address_shift ?this instruction shifts address data into the address register (10 bits) in preparation for either a program or verify instruction. data_shift ?this instruction shifts data into or out of the data register (90 bits), and is used with both the pro- gram and verify instructions. program ?this instruction programs the contents of the data register to the e 2 cmos memory column pointed to by the address register. the device must already be in programming mode for this instruction to execute. prog_incr ?this instruction ?st programs the contents of the data register into e 2 cmos memory column pointed to by the address register and then auto-increments the value of the address register. the device must already be in programming mode for this instruction to execute. program_security ?this instruction programs the electronic security fuse (esf). this prevents data other than the id code and ues strings from being read from the device. the electronic security fuse may only be reset by issuing a bulk_erase command. the device must already be in programming mode for this instruction to exe- cute. xxxx / 0000 0001 0101 0010 / 0000 0100 001 / 1 msb lsb part number (16 bits) 0152h = ispclock5510 (3.3v version) version (4 bits) e 2 configured jedec manufacturer identity code for lattice semiconductor (11 bits) constant ? (1 bit) per 1149.1-1990 xxxx / 0000 0001 0101 0000 / 0000 0100 001 / 1 msb lsb part number (16 bits) 0150h = ispclock5520 (3.3v version) version (4 bits) e 2 configured jedec manufacturer identity code for lattice semiconductor (11 bits) constant ? (1 bit) per 1149.1-1990
lattice semiconductor ispclock5500 family data sheet 40 verify ?this instruction loads data from the e 2 cmos array into the column register. the data may then be shifted out. the device must already be in programming mode for this instruction to execute. verify_incr ?this instruction copies the e 2 cmos column pointed to by the address register into the data col- umn register and then auto-increments the value of the address register. the device must already be in program- ming mode for this instruction to execute. discharge ?this instruction is used to discharge the internal programming supply voltage after an erase or pro- gramming cycle and prepares ispclock5500 for a read cycle. program_usercode ?this instruction writes the contents of the ues register (32 bits) into e 2 cmos memory. the device must already be in programming mode for this instruction to execute. usercode ?this instruction both reads the ues string (32 bits) from e 2 cmos memory into the ues register and addresses the ues register so that this data may be shifted in and out. highz ?this instruction forces all outputs into a high-z state. clamp ?this instruction drives i/o pins with the contents of the boundary scan register. user_logic_reset ?this instruction resets all user-accessible logic, similar to asserting a high on the reset pin. intest ?this instruction performs in-circuit functional testing of the device. erase_done ?this instruction erases the ?one bit only. this instruction is used to disable normal operation of the device while in programming mode until a valid con?uration pattern has been programmed. program_done ?this instruction programs the ?one bit only. this instruction is used to enable normal device operation after programming is complete. noop ?this instruction behaves similarly to the clamp instruction.
lattice semiconductor ispclock5500 family data sheet 41 pin descriptions pin name description pin type pin number ispclock5510 48 tqfp ispclock5520 100 tqfp vcco_0 output driver ? vcc power 1 3 vcco_1 output driver ? vcc power 5 7 vcco_2 output driver ? vcc power 9 11 vcco_3 output driver ? vcc power 25 15 vcco_4 output driver ? vcc power 29 19 vcco_5 output driver ? vcc power 51 vcco_6 output driver ? vcc power 55 vcco_7 output driver ? vcc power 59 vcco_8 output driver ? vcc power 63 vcco_9 output driver ? vcc power 67 gndo_0 output driver ? ground gnd 4 6 gndo_1 output driver ? ground gnd 8 10 gndo_2 output driver ? ground gnd 12 14 gndo_3 output driver ? ground gnd 28 18 gndo_4 output driver ? ground gnd 32 22 gndo_5 output driver ? ground gnd 54 gndo_6 output driver ? ground gnd 58 gndo_7 output driver ? ground gnd 62 gndo_8 output driver ? ground gnd 66 gndo_9 output driver ? ground gnd 70 bank_0a clock output driver 0, ? output output 3 5 bank_0b clock output driver 0, ? output output 2 4 bank_1a clock output driver 1, ? output output 7 9 bank_1b clock output driver 1, ? output output 6 8 bank_2a clock output driver 2, ? output output 11 13 bank_2b clock output driver 2, ? output output 10 12 bank_3a clock output driver 3, ? output output 27 17 bank_3b clock output driver 3, ? output output 26 16 bank_4a clock output driver 4, ? output output 31 21 bank_4b clock output driver 4, ? output output 30 20 bank_5a clock output driver 5, ? output output 53 bank_5b clock output driver 5, ? output output 52 bank_6a clock output driver 6, ? output output 57 bank_6b clock output driver 6, ? output output 56 bank_7a clock output driver 7, ? output output 61 bank_7b clock output driver 7, ? output output 60 bank_8a clock output driver 8, ? output output 65 bank_8b clock output driver 8, ? output output 64 bank_9a clock output driver 9, ? output output 69 bank_9b clock output driver 9, ? output output 68 vcca analog vcc for pll circuitry power 13 30 gnda analog ground for pll circuitry gnd 14 31
lattice semiconductor ispclock5500 family data sheet 42 detailed pin descriptions vcco_[0..9], gndo_[0..9] ?these pins provide power and ground for each of the output banks. in the case when an output bank is unused, its corresponding vcco pin may be left unconnected or preferably should be tied to ground. all gndo pins should be tied to ground regardless of whether the associated bank is used or not. when a bank is used, it should be individually bypassed with a capacitor in the range of 0.01 to 0.1uf as close to its vcco and gndo pins as is practical. bank_[0..9]a, bank_[0..9]b ?these pins provide clock output signals. the choice of output divider (v0-v4) and output driver type (cmos, lvds, sstl, etc.) may be selected on a bank-by-bank basis. when the outputs are con- ?ured as pairs of single-ended outputs, output impedance and slew rate may be selected on an output-by-output basis. vccd digital core vcc power 24, 33 47, 71 gndd digital gnd gnd 15, 16, 17, 23, 48 32, 33, 34, 35, 36, 37, 46, 93 vccj jtag interface vcc power 36 74 refa+ clock reference a positive input input 18 38 refa- clock reference a negative input input 19 39 refb+ clock reference b positive input input 42 refb- clock reference b negative input input 41 refsel clock reference select input (lvcmos) input 1 ?3 refvtt termination voltage for reference inputs power 20 40 tdo jtag tdo output line output 35 73 tdi jtag tdi input line input 2 39 84 tck jtag clock input input 38 83 tms jtag mode select input 2 37 82 lock pll lock indicator, low indicates pll lock output 34 72 sgate synchronous output gate input 1 40 85 goe global output enable input 1 42 87 oex output enable 1 input 21 44 oey output enable 2 input 22 45 ps0 pro?e select 0 input 1 44 89 ps1 pro?e select 1 input 1 43 88 pll_bypass pll bypass input 1 47 92 reset reset pll input 41 86 test1 test input 1 - connect to gndd input 46 91 test2 test input 2 - connect to gndd input 45 90 n/c no internal connection n/a 1, 2, 23, 24, 25, 26, 27, 28, 29, 48, 49, 50, 75, 76, 77, 78, 79, 94, 97, 98, 99, 100 reserved factory use only - do not connect n/a 80, 81, 95, 96 1. internal pull-down resistor. 2. internal pull-up resistor. pin descriptions (continued) pin name description pin type pin number ispclock5510 48 tqfp ispclock5520 100 tqfp
lattice semiconductor ispclock5500 family data sheet 43 vcca, gnda ?these pins provide analog supply and ground for the ispclock5500 familys internal analog cir- cuitry, and should be bypassed with a 0.1uf capacitor as close to the pins as is practical. to improve noise immu- nity, it is suggested that the supply to the vcca pin be isolated from other circuitry with a ferrite bead. vccd, gndd ?these pins provide digital supply and ground for the ispclock5500 familys internal digital circuitry, and should be bypassed with a 0.1uf capacitor as close to the pins as is practical. to improve noise immunity it is suggested that the supply to the vccd pins be isolated with ferrite beads. vccj ?this pin provides power and a reference voltage for use by the jtag interface circuitry. it may be set to allow the ispclock5500 family devices to function in jtag chains operating at voltages differing from vccd. refa+, refa-, refb+, refb- ?these input pins provide the inputs for clock signals, and can accommodate either single ended or differential signal protocols by using either just the ? pins, or both the ? and ? pins. two sets of inputs are provided to accommodate the use of different signal sources and redundant clock sources. refsel ?this input pin is used to select which clock input pair (refa+/- or reb+/-) is selected for use as the ref- erence input. when refsel=0, refa+/- is used, and when refsel=1, refb+/- is used. refvtt ?this pin is used to provide a termination voltage for the reference inputs when they are con?ured for sstl or hstl logic, and should be connected to a suitable voltage supply in those cases. tdo, tdi, tck, tms ?these pins comprise the ispclock5500 devices jtag interface. the signal levels for these pins are determined by the selection of the vccj voltage. lock ?this output pin indicates that the devices pll is in a locked condition when it goes low. sgate ?this input pin provides a synchronous gating function for the outputs, which may be enabled on a bank- by-bank basis. when the synchronous gating function is enabled for a given bank, that banks outputs will output a clock signal when the sgate pin is high, and will drive a constant high or low when the sgate pin is low. synchronous gating ensures that when the state of sgate is changed, no partial clock pulses will appear at the outputs. oex , oey ?these pins are used to enable the outputs or put them into a high-impedance condition. each output may be set so that it is always on, always off, enabled by oex or enabled by oey . goe ?global output enable. this pin drives all outputs to a high-impedance state when it is pulled high. goe also controls the internal feedback buffer, so that bringing goe high will cause the pll to lose lock. ps0, ps1 ?these input pins are used to select one of four user-de?ed con?uration pro?es for the device. pll_bypass ?when this pin is pulled low, the v-dividers are driven from the output of the devices vco, and the device behaves as a phase-locked loop. when this pin is pulled high, the v-dividers are driven directly from the output of the m-divider, and the pll functions are effectively bypassed. reset ?when this pin is pulled high, all on-board counters are reset, and lock is lost. test1,test2 ?these pins are used for factory test functions, and should always be tied to ground. n/c ?these pins have no internal connection. we recommend that they be left unconnected. reserved ?these pins are reserved for factory use and should be left unconnected.
lattice semiconductor ispclock5500 family data sheet 44 package diagrams 48-pin tqfp (dimensions in millimeters) exact shape of each corner is optional. to the lowest point on the package body. 7. a1 is defined as the distance from the seating plane base metal lead between 0.10 and 0.25 mm from the lead tip. 1. dimensioning and tolerancing per ansi y14.5 - 1982. these dimensions apply to the flat section of the allowable mold protrusion is 0.254 mm on d1 and e1 datums a, b and d to be determined at datum plane h. 4. dimensions d1 and e1 do not include mold protrusion. 5. the top of package may be smaller than the bottom 8. of the package by 0.15 mm. dimensions. 2. all dimensions are in millimeters. 6. section b-b: 3. 1 b 0.22 0.17 b 0.27 0.16 0.23 0.20 0.09 c c1 0.09 b1 0.17 0.15 0.13 0.20 max. 1.60 0.15 0.75 1.45 e n l0.45 0.50 bsc 0.60 48 e1 e d1 d 9.00 bsc 7.00 bsc 9.00 bsc 7.00 bsc a2 a1 1.35 0.05 symbol a- min. 1.40 - nom. - c a-b d see detail "a" lead finish c seating plane a 3. 0.08 c b 1 c mc b a-b d 3. d 4x 8. e b 3. e d 0.20 gauge plane a1 0.08 c aa2 1.00 ref. l 0.20 min. b 0-7 b h e1 0.25 0.20 d a-b h d1 section b - b detail "a" notes: pin 1 indicator 1 n
lattice semiconductor ispclock5500 family data sheet 45 100-pin tqfp (dimensions in millimeters) b lead finish base metal 5. the top of package may be smaller than the bottom 4. dimensions d1 and e1 do not include mold protrusion. datums a, b and d to be determined at datum plane h. allowable mold protrusion is 0.254 mm on d1 and e1 2. all dimensions are in millimeters. 1. dimensioning and tolerancing per ansi y14.5 - 1982. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from the lead tip. 7. a1 is defined as the distance from the seating plane to the lowest point on the package body. exact shape of each corner is optional. 8. dimensions. of the package by 0.15 mm. 6. section b-b: 3. section b-b b 1 c b c 1 0.16 0.13 0.09 c1 0.50 bsc 0.17 0.09 c b1 0.17 b e 0.15 0.20 0.20 0.23 0.22 0.27 14.00 bsc 16.00 bsc 0.45 n l e1 e 100 0.60 0.75 14.00 bsc 16.00 bsc d1 d 0.05 1.35 a2 a1 1.40 - 1.45 0.15 symbol detail 'a' a1 0.10 c min. a-- nom. 1.60 max. 0.20 min. 1.00 ref. 0-7 l b side view seating plane 0.20 c md a-b b top view 8 e d a 3 d gauge plane see detail 'a' c a a2 0.20 4x a-b h d h 0.25 bottom view 3 3 b e1 e d1 0.20 a-b c d 100x notes: pin 1 indicator
lattice semiconductor ispclock5500 family data sheet 46 part number description ordering information conventional packaging commercial industrial lead-free packaging commercial industrial part number clock outputs supply voltage package pins isppac-clk5510v-01t48c 10 3.3v tqfp 48 isppac-clk5520v-01t100c 20 3.3v tqfp 100 part number clock outputs supply voltage package pins isppac-clk5510v-01t48i 10 3.3v tqfp 48 isppac-clk5520v-01t100i 20 3.3v tqfp 100 part number clock outputs supply voltage package pins isppac-clk5510v-01tn48c 10 3.3v lead-free tqfp 48 isppac-clk5520v-01tn100c 20 3.3v lead-free tqfp 100 part number clock outputs supply voltage package pins isppac-clk5510v-01tn48i 10 3.3v lead-free tqfp 48 isppac-clk5520v-01tn100i 20 3.3v lead-free tqfp 100 isppac-clk55xx x - 01 xxxx x grade i = industrial temp. range c = commercial temp. range package t48 = 48-pin tqfp t100 = 100-pin tqfp tn48 = lead-free 48-pin tqfp tn100 = lead-free100-pin tqfp device number clk5510 clk5520 operating voltage v = 3.3v performance grade 01 = standard device family
lattice semiconductor ispclock5500 family data sheet 47 package options ispclock5510: 48-pin tqfp isppac- clk5510v-01t48c vcco_0 bank_0a bank_0b gndo_0 vcco_1 bank_1a bank_1b gndo_1 vcco_2 bank_2a bank_2b gndo_2 vcca gnda gndd gndd gndd refa+ refa- refvtt oex oey gndd vccd vcco_3 bank_3a bank_3b gndo_3 vcco_4 bank_4a bank_4b gndo_4 vccd lock tdo vccj tms ps0 tck tdi sgate reset goe ps1 test2 test1 pll_bypass gndd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 3 7
lattice semiconductor ispclock5500 family data sheet 48 ispclock5520: 100-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 isppac-clk5520v-01t100c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c reserved reserved n/c n/c n/c n/c n/c reserved reserved vcco_0 bank_0a bank_0b gndo_0 vcco_1 bank_1a bank_1b gndo_1 vcco_2 bank_2a bank_2b gndo_2 vcco_3 bank_3a bank_3b gndo_3 vcco_4 bank_4a bank_4b gndo_4 vcca gnda gndd gndd gndd gndd gndd ref a+ refa- ref vtt refb- ref b+ rfsel oex oey gndd vccd gndd vcco_5 bank_5a bank_5b gndo_5 vcco_6 bank_6a bank_6b gndo_6 vcco_7 bank_7a bank_7b gndo_7 vcco_8 bank_8a bank_8b gndo_8 vcco_9 bank_9a bank_9b gndo_9 vccd lock tdo vccj tms ps0 tck tdi sgate reset goe ps1 test2 test1 pll_bypass gndd

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